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Integration the VLSI Journal

IF2.5
Papers43
Citations1931
Journal Papers 43
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Design of electronic system for linearization of sinusoidal characteristics of cascaded tunneling magneto-resistance sensor
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IF2.5
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deleteRanjan, Ritu; Mandal, Sanjoy
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Multi-agent based minimal-layer via routing algorithm for PCB design
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deleteCao, Jianhao; Cai, Hao; Xu, Ning
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FPGA routing congestion prediction combining DAGNN and GCN
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deleteNie, Tingyuan; Du, Yang; Guo, Da; Zhao, Kun
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Weak signal detection and circuit implementation based on a novel 3D chaotic synchronization system
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deleteYan, Shaohui; Hu, Weitao; Guo, Zihao
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Hardware implementation of a novel chaos-based cryptosystem for secure image transmission
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deleteAmdouni, Rim; Madani, Mahdi; Hajjaji, Mohamed Ali; Bourennane, El Bay; Atri, Mohamed
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An S to Ku band wideband low-voltage low-power up-conversion mixer in 0.18-μm CMOS technology
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deleteChen, Jun-Da; Shen, Liang-Chung
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An efficient architecture of truncated booth multiplier for AI application
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deleteFairoose, P. Shareefa; Mishra, Ashutosh
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Implementation of imprecise multipliers using 2-bit adder for image processing
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deleteAnguraj, Parthibaraj; Krishnan, Thiruvenkadam
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Optimization of fourth order noise transfer function using PSO algorithm for delta sigma modulator
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deleteTwinkle, J. Arockia; Srinivasan, R.; Chandramani, Premanand, V
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MICSim: A modular pre-circuit simulator for mixed-signal compute-in-memory accelerators in CNNs and transformers
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deleteWang, Cong; Chen, Zeming; Huang, Shanshi
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ATSS-PUF with hardware sharing for secure in-situ memory circuit
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deleteZhang, Shutong; Wang, Pengjun; Xv, Mengfan; Chen, Bo; Zhang, Yuejun
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A lossless floating capacitance multiplier based on the single DDCC-
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deleteYucehan, Tolga; Yuce, Erkan; Minaei, Shahram; Psychalinos, Costas
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High accurate approximate adders using hybrid gates
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deleteZhang, Yongqiang; Qin, Jiao; Cheng, Xin; Xie, Guangjun
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High-performance OTFS transmitter on FPGA: A hybrid HLS/VHDL design
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deleteMerouane, Djaballah; Louiza, Ayat; Rabah, Ouchikh; Salah, Azzaz Mohammed
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An Adaptive Congestion-aware Approximate Communication (ACAC) scheme and implementation for Network-on-Chip systems
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deleteZhou, Shize; Fan, Wenjie; Li, Siyue; Xue, Yongqi; Li, Shiping; Deng, Songfeng; Ji, Jinlun; Cheng, Tong; Wang, Xinyu; Li, Li; Fu, Yuxiang
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True random number generator design based on the fractional-order Sprott H chaotic system with statistical validation
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deleteHosbas, Mehmet Ziya; Emin, Berkay; Akgul, Akif; Kacar, Firat
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Efficient, reliable, and secure PUF architecture with temperature invariance and ML attack resilience
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deleteKumar, Nitish; Nehal, Aakif; Singh, Aditya Vikram; Kandpal, Kavindra; Goswami, Manish
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Fine-grained data integration for high throughput and bandwidth-efficient computation on FPGAs
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deleteLiu, Jiyuan; Wang, Baoping; Tang, Yongming; Li, He
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RapidPnR: Accelerating the physical design for FPGAs via design-level parallelism
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deleteWeng, Wanzheng; Zhou, Pingqiang
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Cross-channel image chain scrambling encryption algorithm using two memristor-based twin multi-scroll hyperchaotic systems
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deleteWang, Zhenju; Wang, Cong; Ma, Ping; Zhang, Hongli; Zhang, Shaohua
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