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In-Sensor-Memory Computing for Post-Von Neumann Intelligence: A Perspective
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DOI：10.1007/s40820-026-02191-y.png)
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Abstract
En 中文
The rapid growth of artificial intelligence, ubiquitous sensing, and edge computing is exposing fundamental limitations of conventional von Neumann architectures, in which the physical separation of sensing, memory, and computation leads to excessive data movement, high energy consumption, and latency. As transistor scaling slows in the post-Moore era, architectural innovation has become essential to sustain progress in intelligent systems. In-sensor-memory computing (ISMC) addresses these challenges by co-locating perception, storage, and computation within unified device and system architectures, enabling in situ signal processing, mixed-signal computation, and event-driven intelligence at the data source. Recent advances in memristive and ferroelectric devices, low-dimensional and multifunctional materials, three-dimensional heterogeneous integration, and neuromorphic architectures have significantly expanded the functional scope of ISMC platforms. In parallel, the co-evolution of algorithms—including spiking neural networks, reservoir computing, and neuromorphic compilers—has facilitated the translation of device-level advantages into system-level performance. This perspective surveys the technological foundations, architectural trends, and emerging applications of ISMC, examines global industry–academia–research (IAR) collaboration, and outlines key challenges related to variability, reliability, scalability, and benchmarking. Collectively, ISMC is positioned as a post-von Neumann hardware paradigm for energy-efficient, distributed intelligence.
Keywords:
In-sensor-memory computing (ISMC)
Post-von Neumann intelligence
Neuromorphic hardware
Industry–academia–research (IAR)
Journal
IF:
36.3
Papers:
2.6K
Citations:
3.6W
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