Memory-Optimized Block Compression for High-Speed Memory Testing

Gyeonggyu Park

doi:10.1109/TVLSI.2026.3686478

Memory-Optimized Block Compression for High-Speed Memory Testing

2026-04-28

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DOI：10.1109/TVLSI.2026.3686478

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In memory testing, test vectors are generated by automatic test equipment (ATE) during testing. To detect diverse faults introduced in modern memories, flexibility in implementing diverse test conditions is required. However, the complex operations for test vector generation during testing make it challenging to achieve high-speed testing and high flexibility simultaneously. In vector memory (VM)-based testing, complex operations are mitigated because test vectors are pre-generated and applied directly to the memory under test (MUT) during testing. However, test vector compression is necessary to address the limited capacity and data-loading speed of the VM. Although conventional code-based compression methods for logic testing are applicable to memory test vectors, low compression ratios are observed due to fundamental differences between logic and memory test vectors. To achieve both high-speed testing and high flexibility, a memory-optimized block compression (MOBC) is proposed. Each field, comprising inputs with the same functional role, is compressed independently by exploiting fundamental characteristics of memory test vectors (e.g., field-specific characteristics and timing constraints). On average, a 36.3% higher compression ratio is achieved compared to conventional compression methods. In addition, the MOBC decoder achieves a higher operating frequency than conventional test vector generators, regardless of the test conditions.

Keywords:

Automatic test equipment (ATE)

code-based compression

high-speed memory

memory testing

test compression

Memory-Optimized Block Compression for High-Speed Memory Testing

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