Novel FPGA Technology Mapping for Dual-Output LUTs: Methodology and Application

2026-05-01

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Liuting Shang *

Sheng Lu

Sungyong Jung

Qilian Liang

Chenyun Pan

DOI：10.1109/TCAD.2025.3616069

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Dual-output look-up tables (LUTs) are supported by modern commercial field-programmable gate array (FPGA) architectures. Existing technology mapping usually generates multioutput LUTs by merging single-output LUTs. However, these mapping solutions often fail to fully leverage the multioutput capability. This article proposes a novel FPGA mapping scheme for multioutput logic units, aiming to improve synthesis performance significantly. By introducing new metrics functions, k-input l-output cut (kl-cut) generation method, and methods to add secondary LUT outputs, the proposed approach enables thorough exploration of the design space. Results show that the proposed dual-output LUT synthesis method achieves 30.2% and 34.7% reduction in LUT usage and depth, respectively, outperforming leading-edge dual-output mapping tools. In addition, the proposed mapping scheme is applied to an emerging field-programmable unit, MCluster, proving compatibility and efficiency on non-LUT logic blocks. For the first time, we perform a system-level design flow to demonstrate the benefit of multioutput LUT at the system level and provide critical insights and design trade-offs.

Keywords:

Table lookup

Field programmable gate arrays

Measurement

Logic

Merging

Computer architecture

Delays

Programmable logic devices

Optimization

Microprocessors

Dual-output

field-programmable gate array (FPGA)

mapping

MCluster

synthesis

Novel FPGA Technology Mapping for Dual-Output LUTs: Methodology and Application

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