.png){kind=icon}
.png){kind=icon}
Return
Optimizing 55 nm split-gate memory for compute-in-memory: a focus on floating-gate engineering
.png){kind=icon}
PRE
AI
W
R
K
D
Y
G
M
Q
Z
X
D
I
T
C
D
DOI：10.1088/1674-4926/25060033.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
The escalating need for high-performance artificial intelligence (AI) computing intensifies the "memory bottleneck" of the von Neumann architecture, prompting extensive exploration of computation-in-memory (CIM) solutions. This study is centered on the optimization of a high-efficiency, low-power "L"-shaped split-gate floating-gate (FG) memory for CIM applications. Fabricated on a 55 nm CMOS platform, the memory devices were systematically investigated through wafer acceptance test (WAT), Sentaurus™ simulations and comprehensive evaluations with the DNN + NeuroSim Framework V2.0. Among devices with diverse FG lengths, the 95-nm FG variant exhibits outstanding performance: it achieves a 5.35 V memory window, reaches a maximum conductance of 16.7 μS with excellent linearity under the varying voltage and width pulse scheme (VWPS), realizes 32-state multi-level storage, and attains a 92% training accuracy on the CIFAR-10 dataset using the VGG8 neural network.
Keywords:
compute-in-memory
floating-gate memory
split-gate
CMOS
neural network training
Journal
IF:
5.3
Papers:
277
Citations:
4.0K
Organization
Cited Papers