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Parallel image compression and encryption algorithm with FPGA implementation based on 4D-NEMHCS and LWT
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DOI：10.1088/1402-4896/ae24b9.png)
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Abstract
En 中文
With the rapid growth of digital image data and the increasing demand for transmission, achieving efficient image compression while ensuring data security has become a critical issue in modern information processing. Traditional image compression and encryption algorithms suffer from low processing efficiency and poor adaptability to large-scale data. To address these challenges, this paper designs a parallel image compression and encryption algorithm based on a four-dimensional non-equilibrium multi-wing hyperchaotic system (4D-NEMHCS) and the lifting wavelet transform (LWT) to simultaneously enhance algorithm performance and security. In the compression stage, the low-frequency components of the image are losslessly compressed in parallel after LWT, while the high-frequency components are lossily compressed in parallel. To further ensure security, a High–Low bit scrambling algorithm and S-box substitution are applied to the compressed low-frequency data, and XOR operation is used to encrypt the high-frequency components. In the algorithm design, 12 threads are utilized to deal with the frequency coefficients through LWT parallelly to accelerate the speed of image processing. What’s more, the 4D-NEMHCS and LWT algorithm are implemented on FPGA to make algorithm efficiency. At last, the compression and encryption algorithm are proved in the experiment and results show that the image can be compressed up to 44% and the speedup ratio of the algorithm is improved to 2.79x.
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