Reliability Analysis of the LEON3 Memory Subsystem Under Single-Event Upsets: Cache, AHB Interface, and Memory Controller Vulnerability

doi:10.3390/info17030249

Reliability Analysis of the LEON3 Memory Subsystem Under Single-Event Upsets: Cache, AHB Interface, and Memory Controller Vulnerability

2026-03-03

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DOI：10.3390/info17030249

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This paper presents a register-transfer-level (RTL) fault injection study of the LEON3 processor's internal memory subsystem under single-event upsets (SEUs). The analysis targets four key components: the instruction cache (I-cache), data cache (D-cache), AHB bus control interface, and memory controller (MCTRL), all of which are unprotected in the standard LEON3 configuration. Using the NETFI+ fault injection framework, multi-cycle SEUs are injected into sequential elements across these blocks while executing a memory-intensive benchmark. The results show that the AHB interface is extremely fragile, with every fault causing execution failure. The memory controller, though architecturally invisible, frequently induces precise SPARC V8 traps such as window overflow and illegal instruction through indirect data-path corruption. The data cache is identified as the primary source of silent data corruption (SDC), while the instruction cache exhibits partial natural masking but remains susceptible to control-flow errors. These findings highlight the disproportionate impact of unprotected protocol and controller logic on system reliability and inform targeted hardening strategies for LEON3-based embedded systems in radiation-prone environments.

Keywords:

LEON3

single-event upset (SEU)

NETlist fault injection

cache vulnerability

AMBA AHB protocol

memory controller (MCTRL)

trap analysis

FPGA

soft errors

Reliability Analysis of the LEON3 Memory Subsystem Under Single-Event Upsets: Cache, AHB Interface, and Memory Controller Vulnerability

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