Simulation-Guided Approximate Logic Synthesis Under the Maximum Error Constraint

Chang Meng

doi:10.1109/tcad.2026.3654911

Simulation-Guided Approximate Logic Synthesis Under the Maximum Error Constraint

2026-01-15

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DOI：10.1109/tcad.2026.3654911

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Approximate computing is an effective computing paradigm for improving the energy efficiency of error-tolerant applications. Approximate logic synthesis (ALS) is an automatic process to generate approximate circuits with reduced area, delay, and power while satisfying user-specified error constraints. This article focuses on ALS under the maximum error constraint. As an essential error metric that provides a worst case error guarantee, the maximum error is crucial for many applications such as image processing and machine learning. This work proposes an efficient simulation-guided ALS flow that handles this constraint. It utilizes logic simulation to: 1) prune local approximate changes (LACs) with large errors that violate the error constraint and 2) accelerate the SAT-based LAC selection process. Furthermore, to enhance scalability, our ALS flow iteratively selects a set of promising LACs satisfying the error constraint to improve the efficiency. The experimental results show that compared with the state-of-the-art method, our ALS flow accelerates by $30.6\times $ and further reduces the circuit area and delay by 18.2% and 4.9%, respectively. Notably, our flow scales to large EPFL benchmarks with up to 38 540 nodes, which remain challenging for existing ALS methods tackling the maximum error constraint.

Keywords:

Approximate computing

approximate logic synthesis (ALS)

logic simulation

maximum error

Simulation-Guided Approximate Logic Synthesis Under the Maximum Error Constraint

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