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Single-Mask Embedded Trace Redistribution Layer Technology Using Grayscale Lithography
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DOI：10.1109/TCPMT.2025.3599484.png)
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Abstract
En 中文
This article presents a novel redistribution layer (RDL) technology with embedded trace structures, targeting high-density interconnects for organic interposers and bridge chips in 2.5-D integration. The proposed embedded trace RDL (ETR) adopts grayscale lithography, enabling the simultaneous formation of vias and traces in a single lithography step. This single-mask process reduces manufacturing complexity and cost compared to conventional dual-mask ETR approaches and is compatible with I-line steppers commonly used in advanced packaging. The proposed ETR successfully demonstrates four-stacked vias with a minimum diameter of 1.5 mu m and traces with 2/1 mu m line/space, validating its capability for fine-pitch, multilayer interconnects. Trace width and dielectric thickness variations were within 7.5% and 2.9% of the median, respectively, and critical dimension uniformity was within 5%. Dense traces between two vias were fabricated and compared with conventional semi-additive process (SAP)-based RDL, confirming that the pad-less vias in the proposed ETR enhance interconnection density. Furthermore, the rounded-edge traces, a distinctive feature of the ETR, reduce conductor loss by mitigating current crowding, leading to improved signal transmission bandwidth. Together, these effects increase bandwidth density, making the proposed ETR highly suitable for advanced high-speed, high-density interconnect applications. Finally, to the best of our knowledge, electromigration (EM) testing was conducted on the ETR structure for the first time, demonstrating a 34.2x improvement in mean time-to-failure (MTTF) over SAP-based RDL.
Keywords:
Lithography
Dielectrics
Fabrication
Routing
Bandwidth
Polymers
Gray-scale
Costs
Conductors
Silicon
Advanced packaging
embedded trace
grayscale lithography
high-density interconnect
redistribution layer (RDL)
Journal
IF:
3
Papers:
230
Citations:
8.0K