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Temperature Compensation Asymmetry at Thermal Extremes in 3-D NAND Flash: Physical Mechanisms and State Dependence
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DOI：10.1109/ted.2026.3708111.png)
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Abstract
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This work experimentally isolates the effective behavior of implemented on-chip temperature compensation (TC) in commercial TLC charge-trapping 3-D <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nand</small> using paired distribution-level measurements with TC and without TC in the same readout domain. We evaluate threshold-voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula>) statistics of program states P1–P7 from −55 °C to 125 °C under high-temperature-program/low-temperature-read (HPLR) and low-temperature-program/high-temperature-read (LPHR) trajectories. Although TC stabilizes the mean <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> within the nominal window (0 °C–70 °C), it exhibits a systematic endpoint mismatch outside this range, manifested as undercompensation at low (UCL) temperatures and overcompensation at high (OCH) temperatures. OCH is concentrated in high program states (P5–P7), compressing adjacent-state spacing and reducing the effective read window. By comparing the paired with TC and without TC statistics, we show that the implemented TC correction is mainly temperature dependent and only weakly state dependent, whereas the intrinsic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text {TH}}\text {(}{T}\text {)}$ </tex-math></inline-formula> response is nonlinear, trajectory dependent, and strongly state dependent. Technology computer-aided design (TCAD) simulations further link this mismatch to temperature-regime-dependent charge behavior, including shallow/deep trap-energy occupancy, rate-limited trapping/detrapping and redistribution, Poole–Frenkel (PF)-assisted emission, and mobility degradation under large stored charge. These results distinguish compensation-induced mismatch from intrinsic device drift and motivate state-aware, temperature-region-aware TC calibration for wide-temperature 3-D <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nand</small> read robustness.
Keywords:
3-D nand flash
technology computer-aided design (TCAD)
temperature compensation (TC)
wide-temperature
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3.2
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685
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