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Time-mode sub-threshold delay-locked loop for low-frequency clock generation
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DOI：10.1016/j.mejo.2026.107211.png)
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Abstract
En 中文
This paper investigates leakage-induced phase disturbances in sub-threshold charge-pump delay-locked loops (CPDLLs). We show leakage-induced phase disturbances are periodic and non-negligible. They prevent the DLLs from locking to their reference clock. We further show the inability-to-lock of these CPDLLs can be eliminated by replacing the charge pump/loop filter with an all-digital time-mode proportional-integral (PI) block implemented using a delay line time-to-digital converter and an encoder called pBlock and a bidirectional gated delay line time integrator called iBlock and linearizing the delay line using digital-to-analog converters (DACs) whose transfer characteristics are the opposite of those of the delay line. The linearization of the sub-threshold delay line reinstates the stability of DLLs while the absence of the charge pump/loop filter removes the root cause of leakage-induced phase disturbances. Sub-threshold voltage generators with a digitally tuned output are also proposed to operate the delay line, pBlock, iBlock, and DACs in sub-threshold to both minimize power consumption and allow the loop dynamics of the DLL to be adjustable. Bootstrapping and high-threshold-voltage devices are utilized in the iBlock to ensure its proper operation. The proposed DLL is designed in a TSMC 130 nm 1.2 V CMOS technology with a reduced supply voltage of 0.6 V and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. Simulation results show the DLL locks to a 100 kHz reference clock with no accumulated static phase errors and improved jitter as compared with its charge pump counterpart. The DLL occupies 0.0425 mm2, offers 0.016% normalized root-mean-square jitter, and consumes 305.5 nW.
Keywords:
Sub-threshold delay-locked loop
Sub-threshold current-starved delay line
Charge pump current leakage
Time-mode proportional and integral locking
Time-to-digital converter
Bi-directional gated delay line time integrator
And bootstrapping
Journal
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2.3
Papers:
296
Citations:
4.7K