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Topology Optimization-Based Layer Assignment Method for Fixed-Layer Complex PCBs

delete2026-01-01
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PRE
AI
吴
吴皓莹 (Haoying Wu)
X
Xiao Jiang
F
Fan, Yilun
贺旭 cover
贺旭 (Xu He)
M
Mingyu Liu *
DOI:10.1109/TCPMT.2025.3643187delete
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Abstract

Abstract

En 中文
In the printed circuit board (PCB) design process, how to meet the layer constraint is crucial for reducing manufacturing costs. Reducing the number of topological crossings is a key factor in layer assignment under fixed layers. Conventional algorithms based on local optimization only consider the escape routing or the area routing region, which are unable to meet the layer constraint. State-of-the-art algorithm simultaneously considers both regions through flexible escape directions to reduce the number of topological crossings, whereas the inconsistency of the evaluation model has the potential to impede further optimization. Therefore, we propose a unified topological evaluation model covering both regions and an optimization method based on a sufficient perturbation mechanism to further reduce the number of topological crossings. To address this issue, we first construct internal and external topological evaluation models separately, then synthesize them into a unified model to further decrease the number of topological crossings, which facilitates the assignment of more nets to the given layers without crossings. Finally, through performing via-insertion on unassigned nets, we further increase the number of assigned nets to meet the layer constraint. Compared to the two-phase approach that employs Yan's layer assignment algorithm, the experimental results show that our proposed integrated method improves the ratio of assigned nets by 18%, while reduces the number of vias by 40.9% on average.
Keywords:
Routing
Pins
Manufacturing
Hands
Evaluation models
Signal integrity
Packaging
Costs
Artificial intelligence
Transforms
Global routing
layer assignment
printed circuit board (PCB)
via minimization

Journal

IEEE Transactions on Components Packaging and Manufacturing Technology cover
IEEE Transactions on Components Packaging and Manufacturing Technology
IF:
3
Papers:
230
Citations:
8.0K

Organization

A
australian national university
Scholars:
2.3K
Papers: 1.2K
Citations: 0
W
wuhan university of technology
Scholars:
8.3K
Papers: 2.4K
Citations: 0
H
hunan university
Scholars:
4.5W
Papers: 3.3W
Citations: 70
H
huazhong university of science & technology
Scholars:
6.1K
Papers: 1.6K
Citations: 0
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Cited Papers

Cited Papers

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Escaped Boundary Pins Routing for High-Speed Boards
err2013-03-01
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errChing-Yu Chin; Chung-Yi Kuan; Tsung-Ying Tsai; Hung-Ming Chen; Yoji Kajitani
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On routing fixed escaped boundary pins for high speed boards
err2011-03-01
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PREAI
errTsung-Ying Tsai,; Ren-Jie Lee,; Ching-Yu Chin,; Chung-Yi Kuan,; Hung-Ming Chen,; Kajitani,Y
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