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J

Josep Torrellas

University of Illinois System

63H-index
650Paper Count
1.4WCitation Count
Published Papers 16
Publication Date
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GRANII: Selection and Ordering of Primitives in GRAph Neural Networks using Input Inspection
err2026 IEEE/ACM INTERNATIONAL SYMPOSIUM ON CODE GENERATION AND OPTIMIZATION, CGO
IF0
err2026-01-01
err0
PREAI
errLenadora, Damitha; Sathia, Vimarsh; Gerogiannis, Gerasimos; Yesil, Serif; Torrellas, Josep; Mendis, Charith
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Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication
errIEEE TRANSACTIONS ON COMMUNICATIONS
IF8.3
err2020-05-01
err25
errOAAI
errTimoneda, Xavier; Abadal, Sergi; Franques, Antonio; Manessis, Dionysios; Zhou, Jin; Torrellas, Josep; Alarcon, Eduard; Cabellos-Aparicio, Albert
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Control Systems for Computing Systems: Making computers efficient with modular, coordinated, and robust control
errIEEE CONTROL SYSTEMS MAGAZINE
IF6.3
err2020-04-01
err6
errOAAI
errPradyumna, Pothukuchi Raghavendra; Pothukuchi, Sweta Yamini; Voulgaris, Petros G.; Torrellas, Josep
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errSave
Medium Access Control in Wireless Network-on-Chip: A Context Analysis
errIEEE COMMUNICATIONS MAGAZINE
IF8.2
err2018-06-01
err48
errOAAI
errAbadal, Sergi; Mestres, Albert; Torrellas, Josep; Alarcon, Eduard; Cabellos-Aparicio, Albert
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errSave
OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture
errIEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
IF6
err2018-03-01
err37
errOAAI
errAbadal, Sergi; Torrellas, Josep; Alarcon, Eduard; Cabellos-Aparicio, Albert
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errSave
Extreme-scale computer architecture
errNATIONAL SCIENCE REVIEW
IF17.1
err2016-01-06
err3
errOAAI
errTorrellas, Josep
errShare
errSave
The Bulk Multicore Architecture for Improved Programmability
errCOMMUNICATIONS OF THE ACM
IF12.2
err2009-12-01
err7
PREAI
errTorrellas, Josep; Ceze, Luis; Tuck, James; Cascaval, Calin; Montesinos, Pablo; Ahn, Wonsun; Prvulovic, Milos
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errSave
Two Hardware-Based Approaches for Deterministic Multiprocessor Replay
errCOMMUNICATIONS OF THE ACM
IF12.2
err2009-06-01
err24
errOAAI
errHower, Derek R.; Montesinos, Pablo; Ceze, Luis; Hill, Mark D.; Torrellas, Josep
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errSave
Automatic code mapping on an intelligent memory architecture
errIEEE TRANSACTIONS ON COMPUTERS
IF3.8
err2001-01-01
err14
PREAI
errSolihin, Y; Lee, JJ; Torrellas, J
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errSave
Comprehensive hardware and software support for operating systems to exploit MP memory hierarchies
errIEEE TRANSACTIONS ON COMPUTERS
IF3.8
err1999-05-01
err2
PREAI
errXia, C; Torrellas, J
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errSave
A chip-multiprocessor architecture with speculative multithreading
errIEEE TRANSACTIONS ON COMPUTERS
IF3.8
err1999-01-01
err159
PREAI
errKrishnan, V; Torrellas, J
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errSave
Excel-NUMA: Toward programmability, simplicity, and high performance
errIEEE TRANSACTIONS ON COMPUTERS
IF3.8
err1999-01-01
err0
PREAI
errZhang, Z; Cintra, M; Torrellas, J
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errSave
Optimizing the instruction cache performance of the operating system
errIEEE TRANSACTIONS ON COMPUTERS
IF3.8
err1998-01-01
err11
PREAI
errTorrellas, J; Xia, C; Daigle, RL
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errSave
The performance of the cedar multistage switching network
errIEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
IF6
err1997-04-01
err7
PREAI
errTorrellas, J; Zhang, Z
errShare
errSave
Data forwarding in scalable shared-memory multiprocessors
errIEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
IF6
err1996-01-01
err33
PREAI
errKoufaty, DA; Chen, XF; Poulsen, DK; Torrellas, J
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errSave
From Colocation to Exfiltration: Practical Cache Side-Channel Attacks in the Modern Public Cloud
errIEEE Micro
IF2.9
err
err0
PREAI
errZirui Neil Zhao; Adam Morrison; Christopher W. Fletcher; Josep Torrellas
errShare
errSave

Research Directions

No research directions
Co-authors
Cooperation Journals
M
Mark D. Hill
H-index: 79 · Papers: 377
L
Luís Ceze
H-index: 61 · Papers: 1.2K
E
Eduard Alarcón
H-index: 43 · Papers: 484
A
Albert Cabellos‐Aparicio
H-index: 42 · Papers: 270
Y
Yan Solihin
H-index: 40 · Papers: 196
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