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Guido Masera

Politecnico di Torino

23H-index
363Paper Count
2.8KCitation Count
Published Papers 42
Publication Date
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QUINN: Quantized Inference and Dataflow Characterization for Neural Networks on RISC-V Near-Memory Architectures
errComputers
IF4.2
err2026-10-01
err0
errOAAI
errVincenzo Petrolo; Flavia Guella; Guido Masera; Maurizio Martina
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PolHEEPo: A 65 nm 6mm2 RISC-V SoC Filling the Gap Between Cloud and Edge Computing
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2026-09-18
err0
PREAI
errLuigi Giuffrida; Alessandra Dolmeta; Alessio Naclerio; Valeria Piscopo; Mattia Mirigaldi; Enrico Manfredi; Alessandro Varaldi; Vincenzo Petrolo; Flavia Guella; Marco Vacca; Guido Masera; Maurizio Martina
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errSave
ANT-V: A Monolithic RISC-V Vector Processor for Machine Learning at the Edge
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2026-09-14
err0
PREAI
errFlavia Guella; Alessio Caviglia; Michele Caon; Stefano Di Carlo; Guido Masera; Maurizio Martina
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errSave
TOXOS: Spinning Up Nonlinearity in On-Vehicle Inference with a RISC-V CORDIC Coprocessor
errTechnologies
IF3.6
err2026-03-03
err0
errOAAI
errLuigi Giuffrida; Guido Masera; Maurizio Martina
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errSave
A High-Entropy True Random Number Generator with Keccak Conditioning for FPGA
errSENSORS
IF3.5
err2025-03-08
err0
errOAAI
errPiscopo, Valeria; Dolmeta, Alessandra; Mirigaldi, Mattia; Martina, Maurizio; Masera, Guido
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MARLIN: A Co-Design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2024-05-01
err4
errOAAI
errGuella, Flavia; Valpreda, Emanuele; Caon, Michele; Masera, Guido; Martina, Maurizio
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ATHOS: A Hybrid Accelerator for PQC CRYSTALS-Algorithms Exploiting New CV-X-IF Interface
errIEEE ACCESS
IF3.6
err2024-01-01
err0
errOAAI
errDolmeta, Alessandra; Martina, Maurizio; Masera, Guido
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Architectural Comparison Model for Area-Efficient PMAP Turbo-Decoders
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2023-01-01
err0
PREAI
errFavero, Simone; Martina, Maurizio; Masera, Guido
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errSave
A Flexible NTT-Based Multiplier for Post-Quantum Cryptography
errIEEE ACCESS
IF3.6
err2023-01-01
err2
errOAAI
errKoleci, Kristjane; Mazzetti, Paolo; Martina, Maurizio; Masera, Guido
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LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor
err2022 IEEE/RSJ INTERNATIONAL CONFERENCE ON INTELLIGENT ROBOTS AND SYSTEMS (IROS)
IF0
err2022-10-23
err7
errOAAI
errViale, Alberto; Marchisio, Alberto; Martina, Maurizio; Masera, Guido; Shafique, Muhammad
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errSave
Efficient Hardware Implementation of the LEDAcrypt Decoder
errIEEE ACCESS
IF3.6
err2021-01-01
err4
errOAAI
errKoleci, Kristjane; Santini, Paolo; Baldi, Marco; Chiaraluce, Franco; Martina, Maurizio; Masera, Guido
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errSave
Low-Complexity Reconfigurable DCT-V Architecture
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2020-12-01
err1
PREAI
errKello, Jurgen; Roch, Massimo Ruo; Masera, Guido; Martina, Maurizio
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errSave
Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis
errSENSORS
IF3.5
err2020-03-04
err2
errOAAI
errPeloso, Riccardo; Capra, Maurizio; Sole, Luigi; Roch, Massimo Ruo; Masera, Guido; Martina, Maurizio
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errSave
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead
errIEEE ACCESS
IF3.6
err2020-01-01
err126
errOAAI
errCapra, Maurizio; Bussolino, Beatrice; Marchisio, Alberto; Masera, Guido; Martina, Maurizio; Shafique, Muhammad
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errSave
Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World
errFUTURE INTERNET
IF3.6
err2019-04-23
err78
errOAAI
errCapra, Maurizio; Peloso, Riccardo; Masera, Guido; Roch, Massimo Ruo; Martina, Maurizio
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errSave
A Multi-Kernel Multi-Code Polar Decoder Architecture
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2018-12-01
err9
errOAAI
errCoppolino, Gabriele; Condo, Carlo; Masera, Guido; Gross, Warren J.
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errSave
Analysis of HEVC transform throughput requirements for hardware implementations
errSIGNAL PROCESSING-IMAGE COMMUNICATION
IF2.7
err2017-09-01
err6
errOAAI
errMasera, Maurizio; Fiorentin, Lorenzo Re; Masala, Enrico; Masera, Guido; Martina, Maurizio
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errSave
Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator
errIEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
IF7.2
err2016-05-01
err8
errOAAI
errGuerrieri, Lorenzo; Masera, Guido; Stievano, Igor S.; Bisaglia, Paola; Valverde, Williams Richard Garcia; Concolato, Mara
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Comments on Bitwise Log-Likelihood Ratios for Quadrature Amplitude Modulations
errIEEE COMMUNICATIONS LETTERS
IF4.4
err2015-11-01
err0
PREAI
errPapaharalabos, Stylianos; Mathiopoulos, P. Takis; Martina, Maurizio; Masera, Guido
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errSave
Unequal Error Protection of Memories in LDPC Decoders
errIEEE TRANSACTIONS ON COMPUTERS
IF3.8
err2015-10-01
err6
errOAAI
errCondo, Carlo; Masera, Guido; Montuschi, Paolo
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Research Directions

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Co-authors
Cooperation Journals
M
Muhammad Shafique
H-index: 49 · Papers: 826
W
Warren J. Gross
H-index: 46 · Papers: 429
D
David Atienza
H-index: 46 · Papers: 605
E
Emanuele Viterbo
H-index: 44 · Papers: 461
P
P. Takis Mathiopoulos
H-index: 40 · Papers: 303
View more