未登录A data-centric chip design agent framework for Verilog code generation用于Verilog代码生成的以数据为中心的芯片设计代理框架
Chang, Kaiyan; Zhu, Wenlong; Wang, Kun; He, Xinyang; Yang, Nan; Chen, Zhirong; Jin, Dantong; Li, Cangyuan; Zhou, Yunhao; Yan, Hao; Zhao, Zhuoliang; Cheng, Yuan; Wang, Mengdi; Liang, Shengwen; Han, Yinhe; Li, Xiaowei; Li, Huawei; Wang, Ying .png)
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