José Luis Imaña - Publications, H-index & Citations

José Luis Imaña

Complutense University of Madrid

11H指数

53论文数

558被引数

收录论文 16

发表时间

Low-Complexity Hardware Architecture of APN Permutations Using TU-Decomposition

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2024-12-01

OAAI

Budaghyan, Lilya; Imana, Jose L.; Kaleyski, Nikolay

In-line rate encrypted links using pre-shared post-quantum keys and DPUs

SCIENTIFIC REPORTS

IF3.9

2024-09-11

OAAI

Aguilera, Abraham Cano; Garcia, Carlos Rubio; Lawo, Daniel; Imana, Jose Luis; Monroy, Idelfonso Tafur; Olmos, Juan Jose Vegas

Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration 具有risc-v集成的NIST三项式的高效低延迟乘法架构

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2024-08-01

OAAI

Imana, Jose L.; Pinuel, Luis; Kuo, Yao-Ming; Ruano, Oscar; Garcia-Herrero, Francisco

Falcon/Kyber and Dilithium/Kyber Network Stack on Nvidia’s Data Processing Unit Platform

IEEE ACCESS

IF3.6

2024-01-01

OAAI

Lawo, D. C.; Frantz, R.; Aguilera, A. Cano; Clemente, X. Arnal, I; Podles, M. P.; Imana, Jose L.; Monroy, I. Tafur; Olmos, J. J. Vegas

Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography 基于倒二进制环LWE的后量子密码的高效硬件算法

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2022-08-01

OAAI

Imana, Jose L.; He, Pengzhou; Bao, Tianyou; Tu, Yazheng; Xie, Jiafeng

Low-Delay FPGA-Based Implementation of Finite Field Multipliers

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2021-08-01

OAAI

Imana, Jose L.

Efficient Hardware Implementation of Finite Field Arithmetic AB plus C for Binary Ring-LWE Based Post-Quantum Cryptography 基于二进制环-LWE的后量子密码有限域算术AB + C的高效硬件实现

IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING

IF5.4

2021-01-01

OAAI

Xie, Jiafeng; He, Pengzhou; Wang, Xiaofang Maggie; Imana, Jose L.

LFSR-Based Bit-Serial GF(2m) Multipliers Using Irreducible Trinomials 使用不可约三项式的基于LFSR的位串行GF(2m) 乘法器

IEEE TRANSACTIONS ON COMPUTERS

IF3.8

2020-01-01

OAAI

Imana, Jose L.

Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials

IEEE TRANSACTIONS ON COMPUTERS

IF3.8

2018-06-01

OAAI

Imana, Jose L.

High-Speed Polynomial Basis Multipliers Over GF(2m) for Special Pentanomials

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2016-01-01

OAAI

Imana, Jose L.

Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

IF7.2

2013-01-01

115

PREAI

Sutter, Gustavo D.; Deschamps, Jean-Pierre; Luis Imana, Jose

Efficient Polynomial Basis Multipliers for Type-II Irreducible Pentanomials

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2012-11-01

PREAI

Imana, Jose L.

Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

IF7.2

2011-07-01

PREAI

Sutter, Gustavo D.; Deschamps, Jean-Pierre; Luis Imana, Jose

Low Latency GF(2m) Polynomial Basis Multiplier

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2011-05-01

PREAI

Luis Imana, Jose

Bit-parallel finite field multipliers for irreducible trinomials 不可约三项式的位并行有限域乘法器

IEEE TRANSACTIONS ON COMPUTERS

IF3.8

2006-05-01

PREAI

Imaña, JL; Sánchez, JM; Tirado, F

Streaming potential across cation-exchange membranes in methanol-water electrolyte solutions

JOURNAL OF COLLOID AND INTERFACE SCIENCE

IF9.7

2006-02-01

PREAI

Barragán, VM; Ruiz-Bauzá, C; Imaña, JL

研究方向