Jiafeng Xie - Publications, H-index & Citations

Jiafeng Xie

Villanova University

20H指数

91论文数

1.0K被引数

收录论文 20

发表时间

ISCAS Guest Editorial Special Issue Based on the 2025 IEEE International Symposium on Circuits and Systems

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2025-12-01

PREAI

Xie, Jiafeng; Du, Yuan; Zhang, Xinmiao

EMINEM: Efficient FPGA Implementation of Mixed-RadIx NTT Hardware AccElerators for NIST Post-QuantuM Cryptography FALCON, Dilithium, and HAWK EMINEM：适用于NIST后量子密码算法Falcon、Dilithium和HAWK的高效FPGA实现混合基数数论变换（NTT）硬件加速器

ACM Transactions on Reconfigurable Technology and Systems

IF2.8

2025-12-01

PREAI

Tu, Yazheng; Xie, Jiafeng

CHIRP: C ompact and H igh-Performance FPGA Implementation of Un i fied Hardware Accelerators for R ing-Binary-LWE-based P QC CHIRP：基于环二进制LWE的PQC统一硬件加速器的紧凑型高性能FPGA实现

ACM Transactions on Reconfigurable Technology and Systems

IF2.8

2025-01-28

PREAI

Tianyou Bao; Pengzhou He; Daisuke Fujimoto; Yuichi Hayashi; Jiafeng Xie

LTE: Lightweight and Timing-Efficient Unequal-Sized Polynomial Multiplication Accelerators

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2025-01-01

PREAI

Tu, Yazheng; Bao, Tianyou; He, Pengzhou; Sousa, Leonel; Xie, Jiafeng

HSPA: High-Throughput Sparse Polynomial Multiplication for Code-based Post-Quantum Cryptography HSPA：基于码的高吞吐量稀疏多项式乘法用于后量子密码学

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS

IF2.6

2024-12-10

PREAI

He, PZ; Tu, YZ; Bao, TY; Koc, CC; Xie, JF

AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC AEKA: 基于环形二进制LWE的轻量级PQC的面积高效Karatsuba加速器的FPGA实现

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS

IF2.8

2024-04-30

OAAI

Bao, Tianyou; He, Pengzhou; Xie, Jiafeng; Jacinto, H. S.

Hardware Circuits and Systems Design for Post-Quantum Cryptography-A Tutorial Brief

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2024-03-01

OAAI

Xie, Jiafeng; Zhao, Wenfeng; Lee, Hanho; Roy, Debapriya Basu; Zhang, Xinmiao

FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography 基于环-二进制-LWE的后量子密码的紧凑型硬件加速器的FPGA实现

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS

IF2.8

2023-06-21

OAAI

He, Pengzhou; Bao, Tianyou; Xie, Jiafeng; Amin, Moeness

Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography 基于倒二进制环LWE的后量子密码的高效硬件算法

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2022-08-01

OAAI

Imana, Jose L.; He, Pengzhou; Bao, Tianyou; Tu, Yazheng; Xie, Jiafeng

Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor

IEEE ACCESS

IF3.6

2022-01-01

OAAI

Lee, Chiou-Yng; Zeghid, Medien; Sghaier, Anissa; Ahmed, Hassan Yousif; Xie, Jiafeng

Novel Low-Complexity Polynomial Multiplication Over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography 混合域上新的低复杂度多项式乘法，用于有效实现二进制Ring-LWE后量子密码

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS

IF3.8

2021-06-01

PREAI

He, Pengzhou; Guin, Ujjwal; Xie, Jiafeng

Efficient Hardware Implementation of Finite Field Arithmetic AB plus C for Binary Ring-LWE Based Post-Quantum Cryptography 基于二进制环-LWE的后量子密码有限域算术AB + C的高效硬件实现

IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING

IF5.4

2021-01-01

OAAI

Xie, Jiafeng; He, Pengzhou; Wang, Xiaofang Maggie; Imana, Jose L.

Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2019-01-01

PREAI

Lee, Chiou-Yng; Xie, Jiafeng

Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2m)

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2018-08-01

PREAI

Shao, Qiliang; Hu, Zhenji; Basha, Shaik Nazeem; Zhang, Zhiping; Wu, Zhiqiang; Lee, Chiou-Yng; Xie, Jiafeng

Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field

IEEE ACCESS

IF3.6

2018-01-01

OAAI

Lee, Chiou-Yng; Fan, Chia-Chen; Xie, Jiafeng; Yuan, Shyan-Ming

Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over G F (2m) Based on NIST Polynomials

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2017-07-01

OAAI

Xie, Jiafeng; Meher, Pramod Kumar; Sun, Mingui; Li, Yuecheng; Zeng, Bo; Mao, Zhi-Hong

High-Throughput Digit-Level Systolic Multiplier Over GF(2m) Based on Irreducible Trinomials

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2015-05-01

PREAI

Xie, Jiafeng; Meher, Pramod Kumar; Mao, Zhi-Hong

Low-Latency High-Throughput Systolic Multipliers Over GF(2m) for NIST Recommended Pentanomials

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2015-03-01

PREAI

Xie, Jiafeng; Meher, Pramod Kumar; Mao, Zhi-Hong

High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2015-01-01

PREAI

Xie, Jiafeng; Meher, Pramod Kumar; Mao, Zhi-Hong

Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic 基于分布式算法的素数长度DCT的硬件高效实现

IEEE TRANSACTIONS ON COMPUTERS

IF3.8

2013-06-01

PREAI

Xie, Jiafeng; Meher, Pramod Kumar; He, Jianjun

研究方向