未登录A data-centric chip design agent framework for Verilog code generation用于Verilog代码生成的以数据为中心的芯片设计代理框架
Chang, Kaiyan; Zhu, Wenlong; Wang, Kun; He, Xinyang; Yang, Nan; Chen, Zhirong; Jin, Dantong; Li, Cangyuan; Zhou, Yunhao; Yan, Hao; Zhao, Zhuoliang; Cheng, Yuan; Wang, Mengdi; Liang, Shengwen; Han, Yinhe; Li, Xiaowei; Li, Huawei; Wang, Ying .png)
分享.png)
收藏AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language ModelsAutoSilicon: 扩大大型语言模型的RTL设计生成能力Li, Cangyuan; Chen, Chujie; Pan, Yudong; Xu, Wenjun; Liu, Yiqi; Chang, Kaiyan; Wang, Yujie; Wang, Mengdi; Li, Huawei; Han, Yinhe; Wang, Ying 分享 收藏 
.png){kind=icon}
.png){kind=icon}
.png){kind=icon}
.png){kind=icon}
