未登录A field-programmable gate array based on wafer-scale 2D semiconductor基于晶圆级2D半导体的现场可编程门阵列
Sun, Qicheng; Ao, Mingrui; Dong, Xiangqi; Shi, Kaichuang; Gou, Saifei; Zhu, Yuxuan; Zhang, Zhejia; Zhang, Jinshu; Hu, Yan; Sun, Zhengjie; Chen, Xinyu; Wang, Lingli; Bao, Wenzhong; Zhou, Peng .png)
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收藏分享 收藏 A RISC-V 32-bit microprocessor based on two-dimensional semiconductors基于二维半导体的RISC-V 32位微处理器Ao, Mingrui; Zhou, Xiucheng; Kong, Xinjie; Gou, Saifei; Chen, Sifan; Dong, Xiangqi; Zhu, Yuxuan; Sun, Qicheng; Zhang, Zhejia; Zhang, Jinshu; Zhang, Qiran; Hu, Yan; Sheng, Chuming; Wang, Kaixuan; Wang, Shuiyuan; Wan, Jing; Han, Jun; Bao, Wenzhong 分享 收藏 First demonstration of monolithic CMOS based on 4-inch three-layer MoTe2首次基于4英寸三层MoTe2的单片CMOS演示Hu, Yan; Sheng, Chuming; Zhang, Zhejia; Sun, Qicheng; Zhang, Jinshu; Gou, Saifei; Dong, Xiangqi; Ao, Mingrui; He, Xinliu; Chen, Haojie; Wang, Die; Song, Yufei; Shang, Jieya; Wang, Xinyu; Zhang, Yue; Zhou, Jingjie; Wang, Xu; Wang, Yi; Wang, Ruixue; Xu, Zihan; Li, Wenwu; Bao, Wenzhong 分享 收藏 Development of Self-Aligned Top-Gate Transistor Arrays on Wafer-Scale Two-Dimensional Semiconductor在晶圆级二维半导体上开发自对准顶栅晶体管阵列Zhu, YX; Zhang, JS; Xie, H; Xia, Y; Dong, XQ; Gou, SF; Zhang, ZJ; He, XL; Chen, HJ; Ao, MR; Sun, QC; Hu, Y; Tian, YC; Shang, JY; Song, YF; Wang, JH; Wang, S; Yue, XF; Cong, CX; Zhou, LH; Dai, S; Xu, ZH; Wan, J; Qiu, HB; Wang, Y; Tan, XJ; Bao, WZ 分享 收藏 High performance Si-MoS2 heterogeneous embedded DRAM高性能Si-MoS2异构嵌入式DRAMXiao, Kai; Wan, Jing; Xie, Hui; Zhu, Yuxuan; Tian, Tian; Zhang, Wei; Chen, Yingxin; Zhang, Jinshu; Zhou, Lihui; Dai, Sheng; Xu, Zihan; Bao, Wenzhong; Zhou, Peng 分享 收藏 Synergistic Engineering of Top Gate Stack for Low Hysteresis 2D MoS2 Transistors低滞后2D MoS2晶体管顶栅叠层的协同工程Sheng, Chuming; Wang, Xinyu; Dong, Xiangqi; Hu, Yan; Zhu, Yuxuan; Wang, Die; Gou, Saifei; Sun, Qicheng; Zhang, Zhejia; Zhang, Jinshu; Ao, Mingrui; Chen, Haojie; Tian, Yuchen; Shang, Jieya; Song, Yufei; He, Xinliu; Xu, Zihan; Li, Lin; Zhou, Peng; Bao, Wenzhong 分享 收藏 分享 收藏 
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