Hsiao-Hsuan Liu - Publications, H-index & Citations

Hsiao-Hsuan Liu

Karlsruhe Institute of Technology

9H指数

35论文数

216被引数

收录论文 4

发表时间

System Scenario-Based Design of the Last-Level Cache in Advanced Interconnect-Dominant Technology Nodes 基于系统场景的高级互连主导技术节点中末级缓存的设计

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS

IF2.6

2025-09-01

OAAI

Mayahinia, Mahta; Marinelli, Tommaso; Pei, Zhenlin; Liu, Hsiao-Hsuan; Pan, Chenyun; Tokei, Zsolt; Catthoor, Francky; Tahoori, Mehdi

Interconnect/Memory Co-Design and Co-Optimization Using Differential Transmission Lines 互连/内存协同设计与协同优化：使用差分传输线

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IF3.1

2025-09-01

PREAI

Zhenlin Pei; Hsiao-Hsuan Liu; Mahta Mayahinia; Mehdi Tahoori; Francky Catthoor; Zsolt Tokei; Prashant Dubey; Chenyun Pan

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2024-12-01

PREAI

Liu, Hsiao-Hsuan; Gilardi, Carlo; Salahuddin, Shairfe M.; Pei, Zhenlin; Schuddinck, Pieter; Xiang, Yang; Weckx, Pieter; Hellings, Geert; Bardon, Marie Garcia; Ryckaert, Julien; Pan, Chenyun; Mitra, Subhasish; Catthoor, Francky

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2024-10-01

PREAI

Pei, Zhenlin; Liu, Hsiao-Hsuan; Mayahinia, Mahta; Tahoori, Mehdi B.; Catthoor, Francky; Tokei, Zsolt; Abdi, Dawit Burusie; Myers, James; Pan, Chenyun

研究方向