Visvesh Sathe - Publications, H-index & Citations

Visvesh Sathe

georgia institute of technology

20H指数

94论文数

1.2K被引数

收录论文 8

发表时间

A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery 32通道85.4 dB SNDR时分复用神经记录前端，实现转换内伪影恢复

IEEE Journal of Solid-State Circuits

IF5.6

2025-12-17

PREAI

Arindam Mandal; Chi-Hsiang Huang; Julian Arenas; Wei-En Lee; Kevin D. Patino-Sosa; Philip Anschutz; Amanda Jacob; Keshav Ramachandra; Samuel Sober; Muhannad S. Bakir; Shaolan Li; Visvesh S. Sathe

A 92.1-dB SNDR Easy-Driving Two-Step NS-SAR-Based Incremental ADC With Concurrent Gain-Error Plus Noise Suppression 一款具有92.1-dB SNDR、Easy-Driving特性，基于两步NS-SAR的增量ADC，并具备并发增益误差与噪声抑制功能。

IEEE Journal of Solid-State Circuits

IF5.6

2025-12-04

PREAI

Chenyang Li; Tzu-Han Wang; Dongsuk Kang; Ken Li; Xitie Zhang; Wei-En Lee; Visvesh S. Sathe; Shaolan Li

A 95.9-dB SNDR 10-kHz BW Third-Order VCO-Based CT ΔΣ Modulator Using a Phase-Time Two-Step Quantizer 一款采用相位-时间两步量化器的95.9-dB SNDR、10-kHz带宽的三阶VCO型连续时间ΔΣ调制器

IEEE Journal of Solid-State Circuits

IF5.6

2025-10-23

PREAI

Ken Li; Wei-En Lee; Xitie Zhang; Tian Xie; Tzu-Han Wang; Visvesh S. Sathe; Shaolan Li

Computational Vector Stimulation for Spatially Targeted, Low-Latency Adaptive Neuromodulation With Common-Mode Artifact Suppression 计算向量刺激在空间靶向、低延迟自适应神经调控中的应用，并抑制共模伪迹

IEEE Transactions on Circuits and Systems I: Regular Papers

IF0

2025-07-03

PREAI

Arindam Mandal; Diego L. Peña-Colaiocco; V. Rajesh Pamula; Steve I. Perlmutter; Forrest Pape; Jacques C. Rudell; Visvesh S. Sathe

A 0.0023 mm2/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression

ieee transactions on circuits and systems i regular papers

IF4.9

2020-04-01

OAAI

Uehlin, John P.; Smith, William Anthony; Pamula, V. Rajesh; Perlmutter, Steve, I; Rudell, Jacques C.; Sathe, Visvesh S.

Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2018-12-01

OAAI

Kim, Sung; Howe, Patrick; Moreau, Thierry; Alaghi, Armin; Ceze, Luis; Sathe, Visvesh S.

Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 Analog Front End With Reduced ADC Resolution Requirements

ieee transactions on circuits and systems i regular papers

IF4.9

2016-12-01

OAAI

Smith, William A.; Mogen, Brian J.; Fetz, Eberhard E.; Sathe, Visvesh S.; Otis, Brian P.

A Compact, Highly-Digital Sensor-Fusion-Based Joint V_dd-Temperature Sensor for SoC Thermal Management 一种紧凑型、高度数字化的基于传感器融合的联合V_dd-温度传感器，用于SoC热管理

IEEE Journal of Solid-State Circuits

IF5.6

PREAI

Hikmet Seha Öztürk; Julian Arenas; Carlos Tokunaga; Nasser Kurd; Visvesh S. Sathe

研究方向