A Post-Routing Layout Optimization Framework for Lithography Process Window Enlargement

doi:10.1109/TCAD.2025.3594247

2025-08-07

PRE

DOI：10.1109/TCAD.2025.3594247

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摘要

En 中文

光刻合规性是保证先进集成电路可制造性的必要条件。增强光刻可成像性的传统流程依赖于光刻临近效应校正（optical proximity correction）和子分辨率辅助特征（SRAF）等技术，这些技术发生在掩模设计阶段。在布局设计后的固定布图和布线方案下，如此晚期设计阶段的优化空间可能极其有限。在本工作中，我们旨在早期设计阶段优化光刻可成像性，并提出了一种后布线布局优化框架，以扩大光刻工艺窗口。该框架利用基于Transformer的深度学习模型进行快速工艺窗口评估，并同时修改布局图案以满足光刻合规性，同时遵循设计规则和连接性约束。实验结果证明了利用我们框架来提高光刻窗口平均4.31%的能力。此外，该框架显著改善了热点布局的优化。

Keyword:

Lithography process window

patch embedding

post-routing layout optimization

process window evaluation (PWE) algorithm

restoration modeling

期刊

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IF:

2.9

论文数:

626

被引数:

9.6K

机构

Institute of Microelectronics of the Chinese Academy of Sciences

学者数:

论文数: 14

被引数: 0

peking university

学者数:

11.9W

论文数: 8.7W

被引数: 146

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