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Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation
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DOI：10.1109/TCSII.2016.2617160.png)
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This brief presents a weighted-based cell segmentation algorithm for a multiple scan-chains built-in self-test in order to reduce the average power consumption when scanning new test vectors and to reduce the test application time. The proposed technique is based on selecting the best group of cells to be connected in the same scan-chain. This group of cells should have the same or very close weight of logic 1s and 0s, which will be optimal to get the highest fault coverage in a specified test length. Then each scan-chain input will be connected to an output of a combinational circuit located after the linear feedback shift register that will generate biased test vectors according to the optimal weight of this segment of cells in the scan-chain. Thus, increasing the fault coverage and smoothing the applied test patterns which will reduce the power consumption. Experimental results on ISCAS' 89 benchmark circuits show that using the proposed design can save on average about 35.75% of the test application time, 30.95% of the average power consumption, which means huge energy saving with an average of 55.6% for 20 ISCAS' 89 benchmark circuits.
Keyword:
Built-in self-test (BIST)
linear feedback shift register (LFSR)
low power test
multiple scan chains
scan cell order
scan segments
scan-based test
weighted switching activity (WSA)
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