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Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique
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DOI：10.1109/TCSI.2015.2469014.png)
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摘要
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Testing the static performances of high-resolution analog-to-digital converters (ADCs) consumes long test times that are disproportionately high with respect to the test time devoted to other types of circuits embedded in a modern system-on-chip (SoC). In this paper, we review the state-of-the-art of reduced-code linearity test methods for pipeline ADCs and we propose a new approach that increases the efficiency and accuracy of the method. We show that by exploiting some inherent properties in the architecture of pipeline ADCs we can achieve significant static test time reduction while maintaining the accuracy of the standard histogram test. The proposed method is demonstrated on a 55 nm 11-bit 2.5-bits/stage pipeline ADC.
Keyword:
Analog-to-digital converter testing
design-for-test
histogram testing
linearity testing
pipeline analog-to-digital converters
reduced-code linearity testing
static testing
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