High-Throughput LDPC Decoder for Multiple Wireless Standards

doi:10.1109/TCSI.2024.3419425

High-Throughput LDPC Decoder for Multiple Wireless Standards

2025-01-01

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DOI：10.1109/TCSI.2024.3419425

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It is a great challenge to design an LDPC decoder with multi-standard compatibility, flexibility and low silicon overhead. This paper presents the efficient and low-overhead design of an LDPC decoder tailored for multi-standard, which include WLAN, 5G NR and WiMAX. We follow the design principles of Application-Specific Instruction-set Processor (ASIP). In order to enhance throughput, we double the computational speed by reducing memory speed from double logic speed to logic speed. By proposing the optimized hybrid scheduling algorithm based on matrix reordering, we further solve scheduling problems and eliminate pipeline conflicts. Through performing logic synthesis utilizing the 28 nm SMIC CMOS cell library, synthesis results show that the core area of our designed decoder is 0.86 mm $<^>{2}$ , the logic gate count is 1716 K, and our design achieves impressive throughput rates, that is up to 9.96 Gbps for WLAN, 7.69 Gbps for WiMAX, and 33 Gbps for 5G NR. Compared with other state-of-the-art LDPC decoders, the experimental results show that our proposed decoder has up to 4.5 x higher throughput, 3.9 $\times$ better area efficiency and 5.8 $\times$ better energy efficiency than these state-of-the-art implementations.

Keywords:

Decoding

Parity check codes

Standards

5G mobile communication

Computer architecture

WiMAX

Wireless LAN

LDPC decoding

multiple standards

ASIP

pipeline conflicts elimination

hybrid scheduling

High-Throughput LDPC Decoder for Multiple Wireless Standards

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