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Scan-Chain Intra-Cell Aware Testing

delete2018-04-01
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A
A. Touati *
A
Alberto Bosio
P
Patrick Girard
A
A. Virazel
P
Paolo Bernardi
M
M. Sonza Reorda
E
Etienne Auvray
DOI:10.1109/TETC.2016.2624311delete
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摘要

摘要

En 中文
This paper first presents an evaluation of the effectiveness of different test pattern sets in terms of ability to detect possible infra-cell defects affecting the scan flip-flops. The analysis is then used to develop an effective test solution to improve the overall test quality. As a major result, the paper demonstrates that by combining test vectors generated by a commercial ATPG to detect stuck-at and delay faults, plus a fragment of extra test patterns generated to specifically target the escaped defects, we can obtain a higher intra-cell defect coverage (i.e., 6.46 percent on average) and a shorter test time (i.e., 42.20 percent on average) than by straightforwardly using an ATPG which directly targets these defects.
Keyword:
Fault simulation
intra-cell defect
scan-chain testing
test quality
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期刊

IEEE Transactions on Emerging Topics in Computing 封面图
IEEE Transactions on Emerging Topics in Computing
IF:
5.4
论文数:
1.1K
被引数:
3.4K

机构

C
centre national de la recherche scientifique (cnrs)
学者数:
24.5W
论文数: 18.2W
被引数: 279
U
universite de montpellier
学者数:
3.8W
论文数: 2.6W
被引数: 46
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