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A New Packaging Design Method for IGBT Modules Based on a Common-Emitter Inductance Decoupling Technology
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DOI：10.1109/TCPMT.2026.3666172.png)
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Abstract
En 中文
This study discusses the phenomenon of V-CE bump that occurs during turn-on transient of insulated gate bipolar transistor (IGBT) due to the disorderly layout of the package, which leads to a significant increase in turn-on energy loss (E-on). This analysis leads to the proposal of common-emitter inductance (CEI) decoupling technology as a solution to mitigate these effects. The effectiveness of the CEI decoupling technique is first validated in discrete device decoupling experiments, where the V-CE bump was suppressed, and E-on was reduced, confirming the principle behind the technology. Experimental results indicate that for every 1-nH reduction in CEI, E-on decreases by approximately 1%. The main focus of the study is on module-level application, where the optimized layout through CEI decoupling technique was tested in a vehicular DC6i IGBT module. Experimental results show that a 55% increase in dI(C)/dt, a 78.9% reduction in E-on, and a 10% current output capability were achieved comparison with standard layout at 150 degrees C. The optimized layout improves switching performance and reduces thermal gradients, leading to better overall thermal management. These results indicate that the proposed method can effectively reduce switching losses and thermal risk, providing a practical solution for the design of high-reliability power modules capable of operating at elevated junction temperatures.
Keywords:
Logic gates
Mathematical models
Insulated gate bipolar transistors
Kelvin
Germanium
Transient analysis
Switches
Layout
Inductance
Pins
Common-emitter inductance (CEI) decoupling technique
insulated gate bipolar transistor (IGBT)
turn-on energy loss (E-on)
V-CE bump
Journal
IF:
3
Papers:
230
Citations:
8.0K