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Adaptive ILT via Multi-Level Lithography Simulation
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DOI：10.1109/TCAD.2025.3561233.png)
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Abstract
En 中文
Inverse lithography technology (ILT) is an advanced resolution enhancement technology (RET) approach that pushes the limits of current process conditions to achieve smaller feature sizes. This article presents an efficient ILT framework centered on the concept of solving mask optimization problem from approximation to precision. First, low-resolution lithography simulation is employed to guide ILT, generating a preliminary solution at a low cost. Subsequently, high-resolution lithography simulation is utilized for fine-tuning, and output the final correction results. Additionally, we introduce a continuous correction scheme and a hyperparameter selection strategy to enhance the adaptability and robustness of the ILT solver for full-chip scale layouts. For via layer patterns, we significantly improve the solver's performance by adopting a new high-resolution ILT approach combined with a restricted optimization region. Experimental results show that our method effectively reduces edge placement error (EPE) violations and improves efficiency for ILT on full-chip scale layouts. In the ICCAD 2013 benchmark, our method outperforms state-of-the-art approaches, reducing L-2 loss by at least 1.3%. For via layer patterns, our method achieves a 98% reduction in L2 loss and nearly triples the runtime efficiency compared to its earlier version. Furthermore, it delivers an 8% reduction in L2 loss and a 45% reduction in PVBand compared to other existing methods.
Keywords:
Lithography
Runtime
Computational modeling
Mathematical models
Semiconductor device modeling
Optimization
Layout
Optical imaging
Shape
Neural networks
Inverse lithography
optical proximity correction
multi-level lithography simulation
Journal
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2.9
Papers:
564
Citations:
9.6K