.png){kind=icon}
.png){kind=icon}
Return
BR-CIM: An Efficient Binary Representation Computation-In-Memory Design
.png){kind=icon}
PRE
AI
DOI：10.1109/TCSI.2022.3185135.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
Deep neural network (DNN) has recently attracted tremendous attention in various fields. But the computing operation requirement and the memory bottleneck limit the energy efficiency of hardware implementations. Binary quantization is proposed to relieve the pressure of hardware design. And the Computing-In-Memory (CIM) is regarded as a promising method to resolve the memory wall challenge. However, the binary computing paradigm is mismatched with the CIM scheme, which incurs complex circuits and peripheral to realize binary operation in previous works. To overcome previous issues, this work presents Binary Representation Computation-In-Memory (BR-CIM) with several key features. (1) A lightweight computation unit is realized within the 6T SRAM array to accelerate binary computing and enlarge signal margin; (2) The reconfigurable computing scheme and mapping method support extendable bit precision to satisfy the accuracy requirement of various applications; (3) Simultaneous computing and weight loading is supported by column circuitry, which shortens the data loading latency; Several experiments are conducted to estimate algorithm accuracy, the computing latency, and power consumption. The energy efficiency reaches up to 1280 TOPs/W for binary representation. And the algorithm accuracy achieves 97.82%/76.4% on MNIST/CIFAR-100 dataset.
Keywords:
Neural networks
Random access memory
Computer architecture
Arrays
Common Information Model (computing)
Quantization (signal)
Microprocessors
Computation-in-memory
artificial intelligence
deep neural network
binary neural network
sram
reconfigurable design
Journal
IF:
5.2
Papers:
9.7K
Citations:
2.2W