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Shouyi Yin

tsinghua university

39H-index
471Paper Count
6.7KCitation Count
Published Papers 83
Publication Date
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GFRA: A High-Utilization Grain-Fused Reconfigurable Architecture for Coarse-Grained and Fine-Grained Applications
errIEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF3.1
err2026-06-16
err0
PREAI
errXiaokai Fang; Jiangyuan Gu; Xunbo Hu; Dan Zhu; Yang Hu; Shouyi Yin
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XY-Serve: End-to-End Versatile Production Serving for Dynamic LLM Workloads
errPROCEEDINGS OF THE 31ST ACM INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS, VOL 1, ASPLOS 2026
IF0
err2026-01-01
err0
PREAI
errSong, Mingcong; Tang, Xinru; Hou, Fengfan; Li, Jing; Wei, Wei; Ma, Yipeng; Xiao, Runqiu; Si, Hongjie; Jiang, Dingcheng; Yin, Shouyi; Hu, Yang; Long, Guoping
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A 77.35 TOPS/W Transformer Processor Exploiting Multi-Scope Similarity in Attention Computing
errIEEE Journal of Solid-State Circuits
IF5.6
err2025-12-10
err0
PREAI
errYang Wang; Yubin Qin; Dazheng Deng; Xiaolong Yang; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Leibo Liu; Shaojun Wei; Yang Hu; Shouyi Yin
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AutoDSRI: An Automated Framework for Domain-Specific Reusable Interposer Based Chiplets Design
errELECTRONICS LETTERS
IF0.8
err2025-10-27
err0
errOAAI
errLiu, Yafei; Li, Xiangyu; Yin, Shouyi
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A Hierarchical-Hybrid Floating-Point Compute-in-Memory Macro Using FP-DAC and FP-ADC for Edge-AI Devices
errIEEE Journal of Solid-State Circuits
IF5.6
err2025-08-29
err0
PREAI
errYuanzhe Zhao; Yang Wang; Rui P. Martins; Chi-Hang Chan; Shouyi Yin; Minglei Zhang
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MRCIM: A Many-Core Reconfigurable Computing-in-Memory Processor Combining CPU and Tensor Modes for NN Acceleration
errieee transactions on circuits and systems i: regular papers
IF0
err2025-08-07
err0
PREAI
errZhen He; Yiqi Wang; Zihan Wu; Huiming Han; Shaojun Wei; Yang Hu; Chao Li; Fengbin Tu; Shouyi Yin
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An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications
errIEEE Journal of Solid-State Circuits
IF5.6
err2025-08-01
err0
PREAI
errYang Wang; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu; Shouyi Yin
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errSave
ETCIM: Error-Tolerant Digital CIM Processor With Redundancy-Free Hard Error Repair and Run-Time Soft Error Correction
errIEEE Journal of Solid-State Circuits
IF5.6
err2025-05-20
err0
PREAI
errYiqi Wang; Zhen He; Chenggang Zhao; Zihan Wu; Mingyu Gao; Huiming Han; Shaojun Wei; Yang Hu; Fengbin Tu; Shouyi Yin
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Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design
errIEEE TRANSACTIONS ON COMPUTERS
IF3.8
err2025-01-01
err0
PREAI
errDeng, Jinyi; Tang, Xinru; Zhang, Jiahao; Li, Yuxuan; Zhang, Linyun; Tu, Fengbin; Wei, Shaojun; Hu, Yang; Yin, Shouyi
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errSave
BeaCIM: A Digital Compute-in-Memory DNN Processor With Bi-Directional Exponent Alignment for FP8 Training
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2025-01-01
err0
PREAI
errZhou, Yang; Wang, Yang; Yin, Wenxin; Jiang, Yazheng; Wei, Jingchuan; Qin, Yubin; Hu, Yang; Wei, Shaojun; Yin, Shouyi
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Review of chiplet-based design: system architecture and interconnection
errSCIENCE CHINA-INFORMATION SCIENCES
IF7.6
err2024-07-19
err0
PREAI
errLiu, Yafei; Li, Xiangyu; Yin, Shouyi
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SWG: an architecture for sparse weight gradient computation
errSCIENCE CHINA-INFORMATION SCIENCES
IF7.6
err2024-01-23
err2
PREAI
errWu, Weiwei; Tu, Fengbin; Li, Xiangyu; Wei, Shaojun; Yin, Shouyi
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Wafer-Scale Computing: Advancements, Challenges, and Future Perspectives [Feature]
errIEEE CIRCUITS AND SYSTEMS MAGAZINE
IF3.5
err2024-01-01
err3
PREAI
errHu, Yang; Lin, Xinhan; Wang, Huizheng; He, Zhen; Yu, Xingmao; Zhang, Jiahao; Yang, Qize; Xu, Zheng; Guan, Sihan; Fang, Jiahao; Shang, Haoran; Tang, Xinru; Dai, Xu; Wei, Shaojun; Yin, Shouyi
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STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2023-06-01
err9
PREAI
errWu, Weiwei; Tu, Fengbin; Niu, Mengqi; Yue, Zhiheng; Liu, Leibo; Wei, Shaojun; Li, Xiangyu; Hu, Yang; Yin, Shouyi
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errSave
Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2023-03-01
err6
PREAI
errWei, Shaojun; Lin, Xinhan; Tu, Fengbin; Wang, Yang; Liu, Leibo; Yin, Shouyi
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SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2023-01-01
err5
PREAI
errWang, Yiqi; Tu, Fengbin; Liu, Leibo; Wei, Shaojun; Xie, Yuan; Yin, Shouyi
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SWPU: A 126.04 TFLOPS/W Edge-Device Sparse DNN Training Processor With Dynamic Sub-Structured Weight Pruning
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2022-10-01
err5
PREAI
errWang, Yang; Qin, Yubin; Liu, Leibo; Wei, Shaojun; Yin, Shouyi
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GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2022-10-01
err12
PREAI
errYang, Jianxun; Tu, Fengbin; Li, Yixuan; Wang, Yiqi; Liu, Leibo; Wei, Shaojun; Yin, Shouyi
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BR-CIM: An Efficient Binary Representation Computation-In-Memory Design
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2022-10-01
err8
PREAI
errYue, Zhiheng; Wang, Yabing; Qin, Yubin; Liu, Leibo; Wei, Shaojun; Yin, Shouyi
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errSave
PL-NPU: An Energy-Efficient Edge-Device DNN Training Processor With Posit-Based Logarithm-Domain Computing
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2022-10-01
err7
PREAI
errWang, Yang; Deng, Dazheng; Liu, Leibo; Wei, Shaojun; Yin, Shouyi
errShare
errSave

Research Directions

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Co-authors
Cooperation Journals
Z
Zhen He
H-index: 87 · Papers: 548
Y
Yuan Xie
H-index: 81 · Papers: 868
王
王栋 (Dong Wang)
H-index: 67 · Papers: 878
Y
Yike Guo
H-index: 66 · Papers: 671
周
周丽 (Li Zhou)
H-index: 64 · Papers: 793
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