.png){kind=icon}
.png){kind=icon}
Return
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture
.png){kind=icon}
PRE
AI
DOI：10.1109/TCSI.2015.2471575.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
In this paper, a design approach for architecture-aware nonbinary low-density parity-check convolutional codes (NB-LDPC-CCs) is presented to jointly optimizes the code performance and decoder complexity for achieving high energy-efficiency decoder. The proposed NB-LDPC-CCs not only feature simple structure and low degree, but also compete with other published NB-LDPC-CCs on error-correction capability. With these codes, we present a memory-based layered decoder architecture, where the computation units and the scheduling of the computations are optimized to increase energy efficiency. To demonstrate the feasibility of proposed techniques, a time-varying (50,2,4) NB-LDPC-CC over GF(256) is constructed, and associated decoder is implemented in 90 nm CMOS. The code can reach BER = 10(-5) at SNR = 0.9 dB, and support multi code rates with puncturing. Comparing with the state-of-the-art designs, the proposed decoder can save 74% power under the same number of iterations, making it suitable for emerging Internet of Things (IoT) applications.
Keywords:
Convolutional codes
error correction
nonbinary low-density parity-check (NB-LDPC) convolutional codes
VLSI
AI Summary
Key information extracted from the uploaded paper, including a brief overview, abstract, background, key highlights, visual analysis, and future outlook.
Journal
IF:
5.2
Papers:
9.7K
Citations:
2.2W