Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing

doi:10.1109/TCSII.2012.2195058

Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing

2012-06-01

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DOI：10.1109/TCSII.2012.2195058

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Nonbinary low-density parity-check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity iterative decoding algorithms have been proposed, the VLSI implementation of NB-LDPC decoders still remains a big challenge due to its high complexity and long latency. In this brief, a highly efficient check node processing scheme, which the processing delay greatly reduced, is proposed for Min-max decoding algorithm. Thereafter, an efficient check node unit (CNU) can be designed. Compared with previous works, the latency of the CNU could be reduced to less than 52%. In addition, a decoder for a (620, 310) NB-LDPC code is designed to demonstrate the efficiency of the presented techniques.

Keywords:

Low-density parity-check (LDPC) codes

min-max decoding

nonbinary

VLSI design

Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing

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