Power Trace-driven 3D-IC Floorplanning

Yihan Wen

doi:10.1109/tcad.2026.3730347

Power Trace-driven 3D-IC Floorplanning

2026-09-03

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DOI：10.1109/tcad.2026.3730347

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Thermal estimation and optimization present a significant challenge in the design of three-dimensional integrated circuits (3D-IC). However, dynamic thermal profiles derived from realistic working scenarios have been neglected during the floorplanning stage so far. Ignoring such time-varying thermal behaviors may lead to suboptimal floorplans, as static or time-averaged thermal models fail to capture the temporal evolution of block-level power distributions under realistic workloads. This paper proposes a power trace-driven floorplanning methodology for 3D-IC that incorporates real functional vectors. First, dynamic power traces are generated through gate-level simulation and vector-based power analysis using functional testbenches. Then, a computationally efficient thermal model based on block-level Green’s functions is proposed to enable dynamic thermal profiling over long power traces. Finally, a thermal dispersion-based perturbation is integrated into the floorplanning process to minimize the peak temperature. Experimental results demonstrate that the proposed floorplanning method effectively reduces the maximum temperature and total wirelength, while maintaining efficient runtime under long dynamic power traces.

Keywords:

3D-IC design & optimization

physical design

floorplanning

thermal modeling

power trace

Power Trace-driven 3D-IC Floorplanning

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