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SaveA data-centric chip design agent framework for Verilog code generation
Chang, Kaiyan; Zhu, Wenlong; Wang, Kun; He, Xinyang; Yang, Nan; Chen, Zhirong; Jin, Dantong; Li, Cangyuan; Zhou, Yunhao; Yan, Hao; Zhao, Zhuoliang; Cheng, Yuan; Wang, Mengdi; Liang, Shengwen; Han, Yinhe; Li, Xiaowei; Li, Huawei; Wang, Ying
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SaveAutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models
Li, Cangyuan; Chen, Chujie; Pan, Yudong; Xu, Wenjun; Liu, Yiqi; Chang, Kaiyan; Wang, Yujie; Wang, Mengdi; Li, Huawei; Han, Yinhe; Wang, Ying
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SaveA self-reported symptom-based decision-making model helps to rule out outpatient cases at low risk for CRC before colonoscopy
Luan, Zhe; Liu, Fangfang; Zhang, Li; Chen, Jun; Zhao, Yiming; Li, Congyong; Liu, Zhaoyun; Li, Huawei; Dong, Li; Zang, Funing; Han, Lingyan; Zhao, Tianyue; Wang, Qiao; Sun, Gang; Wang, Shufang
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