Xin Si - Publications, H-index & Citations

Xin Si

Southeast University

24H指数

79论文数

2.8K被引数

收录论文 13

发表时间

A 512-Kb VCMA–MRAM With PVT-Aware Capacitive-Coupled Readout and Retained-State Burst Operation Achieving 1.12-ns/bit Latency and 14.25-fJ/bit Read Energy 512-Kb VCMA–MRAM器件，具有PVT感知电容耦合读出和保持状态突发操作，实现1.12纳秒/位延迟和14.25飞焦/位读出能量

IEEE Transactions on Circuits and Systems I-Regular Papers

IF5.2

2026-09-10

PREAI

Zeying Ding; Yantong Di; Haoran Du; Huanghui Wang; Yaoru Hou; Bo Liu; Xin Si; Hao Cai

CSUM: A 28-nm Vertical-Feature-Shift and Horizontal-Weight-Shift-Based Separate-WL 6T-SRAM Computing-in-Memory Unit Macro for Edge Depthwise Neural-Networks CSUM: 基于28纳米垂直特征移位和水平权重移位的独立字线6T-SRAM近存储计算单元宏，用于边缘深度分离神经网络

IEEE Journal of Solid-State Circuits

IF5.6

2025-12-17

PREAI

Bo Wang; Zhaoyang Zhang; Feiran Liu; Yuchen Tang; Yuchen Ma; Xiaoxue Zhong; Defa Wu; Tianzhu Xiong; An Guo; Xiaomin Li; Xin Si; Jun Yang

An LSGQ-FFS Framework for Adaptive Optimization of Hybrid INT-CIM Architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IF3.1

2025-11-13

PREAI

Shaochen Li; Xi Chen; Yujia Xiong; Yuhan Liu; Lingyi Kong; He Wang; Tianhui Jiao; Xing Wang; Xiaomin Li; Yan Yan; Yuchen Ma; Xin Si

BooLUT-CIM: A 52.4 TOPS/W Radix-4 Booth-LUT Digital CIM With Negative-Magnitude-Bits Inversion Storage BooLUT-CIM：一种具有52.4 TOPS/W性能的基数4布斯-查找表（LUT）数字CIM，采用负量级位反转存储技术

IEEE Transactions on Circuits and Systems II: Express Briefs

IF0

2025-07-21

OAAI

Yi Yang; Xiao Tan; Jinwu Chen; Yucheng Du; Tianhui Jiao; Xing Wang; An Guo; Xin Si

A 28 nm 128-kb Exponent- and Mantissa-Computation-In-Memory Dual-Macro for Floating-Point and INT CNNs 28 nm工艺下用于浮点数和INT卷积神经网络的128-kb指数和尾数计算存内计算双宏单元

IEEE Journal of Solid-State Circuits

IF5.6

2025-01-01

PREAI

An Guo; Xueshan Dong; Fangyuan Dong; Dongqi Li; Yiran Zhang; Jingmin Zhang; Jun Yang; Xin Si

Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture 基于数字浮点内存计算架构的切换速率感知量化模型

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2024-06-01

PREAI

Chen, Xi; Zhao, Yitong; Guo, An; Chen, Jinwu; Dong, Fangyuan; Zhang, Zhaoyang; Xiong, Tianzhu; Wang, Bo; Kong, Yuyao; Si, Xin

An INT8 Charge-Digital Hybrid Compute-In-Memory Macro With CNN-Friendly Shift-Feed Register Design

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2024-03-01

PREAI

Chen, Jinwu; Zhao, Yitong; Xiong, Tianzhu; Si, Xin

Preparation and quality assessment of processed cream cheese by high hydrostatic pressure combined thermal processing and spore-induced germination

JOURNAL OF FOOD ENGINEERING

IF5.8

2023-03-01

PREAI

Song, Bo; Zhu, Panpan; Zhang, Yumeng; Ju, Ning; Si, Xin; Pang, Xiaoyang; Lv, Jiaping; Zhang, Shuwen

Evaluation Platform of Time-Domain Computing-in-Memory Circuits

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2023-03-01

OAAI

Kong, Yuyao; Chen, Xi; Si, Xin; Yang, Jun

A computing-in-memory macro based on three-dimensional resistive random-access memory 基于三维电阻式随机存取存储器的内存计算宏

NATURE ELECTRONICS

IF40.9

2022-07-26

OAAI

Huo, Qiang; Yang, Yiming; Wang, Yiming; Lei, Dengyun; Fu, Xiangqu; Ren, Qirui; Xu, Xiaoxin; Luo, Qing; Xing, Guozhong; Chen, Chengying; Si, Xin; Wu, Hao; Yuan, Yiyang; Li, Qiang; Li, Xiaoran; Wang, Xinghua; Chang, Meng-Fan; Zhang, Feng; Liu, Ming

Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

IF4.9

2021-05-01

PREAI

Wang, Linfang; Ye, Wang; Dou, Chunmeng; Si, Xin; Xu, Xiaoxin; Liu, Jing; Shang, Dashan; Gao, Jianfeng; Zhang, Feng; Liu, Yongpan; Chang, Meng-Fan; Liu, Qi

A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

IF5.2

2019-11-01

131

PREAI

Si, Xin; Khwa, Win-San; Chen, Jia-Jing; Li, Jia-Fang; Sun, Xiaoyu; Liu, Rui; Yu, Shimeng; Yamauchi, Hiroyuki; Li, Qiang; Chang, Meng-Fan

MPN-S: An Algorithm-Hardware Co-Designed Architecture for High-Efficiency Softmax Computation MPN-S：一种算法-硬件协同设计的用于高效Softmax计算的架构

ieee transactions on circuits and systems ii express briefs

IF0

PREAI

Yuchen Ma; Defa Wu; Yucheng Du; Xing Wang; Xin Si; Chao Chen

研究方向