未登录
分享
收藏
分享
收藏
分享
收藏
分享
收藏
分享
收藏
分享
收藏
分享
收藏
分享
收藏SAP: Shared-Aware Prefetching for Reducing Inter-Chiplet Data Access LatencySAP:一种共享感知预取方法以降低芯片间数据访问延迟
Huang, Junpei; Xu, Haobo; Gan, Yiming; Li, Ying; Sun, Wenhao; Wang, Mengdi; Wei, Xiaotong; Min, Feng; Wang, Ying; Han, Yinhe
分享
收藏
分享
收藏
分享
收藏A data-centric chip design agent framework for Verilog code generation用于Verilog代码生成的以数据为中心的芯片设计代理框架
Chang, Kaiyan; Zhu, Wenlong; Wang, Kun; He, Xinyang; Yang, Nan; Chen, Zhirong; Jin, Dantong; Li, Cangyuan; Zhou, Yunhao; Yan, Hao; Zhao, Zhuoliang; Cheng, Yuan; Wang, Mengdi; Liang, Shengwen; Han, Yinhe; Li, Xiaowei; Li, Huawei; Wang, Ying
分享
收藏AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language ModelsAutoSilicon: 扩大大型语言模型的RTL设计生成能力
Li, Cangyuan; Chen, Chujie; Pan, Yudong; Xu, Wenjun; Liu, Yiqi; Chang, Kaiyan; Wang, Yujie; Wang, Mengdi; Li, Huawei; Han, Yinhe; Wang, Ying
分享
收藏
分享
收藏
分享
收藏
分享
收藏
分享
收藏Controllable Synthesis of Hollow Mesoporous ZSM-5 with Improved Catalytic Performance for Tetralin Hydrocracking to Light Aromatics
Zhang, Haoqing; Zhang, Limin; Wang, Mengdi; Li, Keyan; Zhang, Anfeng; Wang, Hao; Wu, Jiaming; Lin, Shanfan; Li, Duo; Song, Chunshan; Guo, Xinwen
分享
收藏
分享
收藏
分享
收藏