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Radway, Robert M.; Bartolo, Andrew; Jolly, Paul C.; Khan, Zainab F.; Le, Binh Q.; Tandon, Pulkit; Wu, Tony F.; Xin, Yunfeng; Vianello, Elisa; Vivet, Pascal; Nowak, Etienne; Wong, H. -S. Philip; Aly, Mohamed M. Sabry; Beigne, Edith; Wootters, Mary; Mitra, Subhasish
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收藏A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS32 kb 0.35-1.2 V,50 MHz-2.5 GHz位交错SRAM,带有8 t SRAM单元和数据相关写入辅助,采用28 nm utbb-fdsoi CMOS
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