.png){kind=icon}
返回
Practical Strategies for Power-Efficient Computing Technologies
.png){kind=icon}
PRE
AI
DOI：10.1109/JPROC.2009.2035451.png)
.png){kind=icon}
原文求助.png){kind=icon}
分享.png){kind=icon}
收藏
摘要
En 中文
After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an similar to 8 x improvement in power efficiency can be attained without system performance loss in parallelizable applications-those in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.
Keyword:
Circuit optimization
CMOS digital integrated circuits
CMOSFETs
integrated circuit design
integrated circuit interconnections
parallel machines
power distribution
AI总结
对已上传原文的论文进行重点信息的提取，主要内容包括：简要概述、研究摘要、背景介绍、关键亮点、图文解析、展望与总结。
期刊
IF:
25.9
论文数:
9.9K
被引数:
4.5W
机构
引用论文
Suppressed Mobility of Negative Charges in Polymer Electrolytes with an Ether‐Functionalized Anion
OAAI
.png){kind=icon}
OAAI分享收藏
查看更多内容