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SaveShare Save Share Save Share Save Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture
Chen, Xi; Zhao, Yitong; Guo, An; Chen, Jinwu; Dong, Fangyuan; Zhang, Zhaoyang; Xiong, Tianzhu; Wang, Bo; Kong, Yuyao; Si, Xin Share Save Share Save Share Save Share Save A computing-in-memory macro based on three-dimensional resistive random-access memoryHuo, Qiang; Yang, Yiming; Wang, Yiming; Lei, Dengyun; Fu, Xiangqu; Ren, Qirui; Xu, Xiaoxin; Luo, Qing; Xing, Guozhong; Chen, Chengying; Si, Xin; Wu, Hao; Yuan, Yiyang; Li, Qiang; Li, Xiaoran; Wang, Xinghua; Chang, Meng-Fan; Zhang, Feng; Liu, Ming Share Save Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing ControlWang, Linfang; Ye, Wang; Dou, Chunmeng; Si, Xin; Xu, Xiaoxin; Liu, Jing; Shang, Dashan; Gao, Jianfeng; Zhang, Feng; Liu, Yongpan; Chang, Meng-Fan; Liu, Qi Share Save A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge ProcessorsSi, Xin; Khwa, Win-San; Chen, Jia-Jing; Li, Jia-Fang; Sun, Xiaoyu; Liu, Rui; Yu, Shimeng; Yamauchi, Hiroyuki; Li, Qiang; Chang, Meng-Fan Share Save Share Save 
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