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J

Jinshan Yue

chinese academy of sciences

20H-index
109Paper Count
1.4KCitation Count
Published Papers 31
Publication Date
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A 28-nm System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-Over-Logic 1T1C eDRAM
errIEEE Journal of Solid-State Circuits
IF5.6
err2026-04-24
err0
PREAI
errZhihang Qian; Zhaori Cong; Shengzhe Yan; Zeyu Guo; Zhuoyu Dai; Yifan He; Wenyu Sun; Chunmeng Dou; Feng Zhang; Di Geng; Jinshan Yue; Yongpan Liu; Qi Liu; Ming Liu
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A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference
errIEEE Journal of Solid-State Circuits
IF5.6
err2026-04-07
err0
PREAI
errYiyang Yuan; Bingxin Zhang; Yiming Yang; Yishan Luo; Qirui Chen; Haitao Wang; Qihao Liu; Zhiming Chen; Hao Wu; Jinshan Yue; Shidong Lv; Xinghua Wang; Pui-In Mak; Xiaoran Li; Feng Zhang
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A 28-nm Hybrid-Domain Outer Product-Based Floating-Point SRAM Computing-in-Memory Macro With Logarithm Bit-Width Residual ADC for Edge AI
errIEEE Journal of Solid-State Circuits
IF5.6
err2026-03-03
err0
PREAI
errYiyang Yuan; Zhongyi Sun; Yiming Yang; Xinghua Wang; Xiaoran Li; Cailian Ma; Qirui Chen; Meini Tang; Xi Wei; Hao Wu; Haitao Wang; Qihao Liu; Chengying Chen; Jinshan Yue; Pui-In Mak; Feng Zhang
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A hybrid-tiling attention accelerator with a fully-pipelined balanced systolic array in 3D hybrid-bonding near-DRAM integration
errMicroelectronics Journal
IF2.3
err2026-02-01
err0
PREAI
errHan, Zhongze; Gao, Hanghang; Li, Weizeng; Li, Zhi; Zhou, Zhidao; Wang, Yiman; Shen, Junzhe; Zhu, Junyu; Wang, Bohan; Yang, Jianguo; Yue, Jinshan; Hu, Hongyang; Dou, Chunmeng
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A 14-nm Nonvolatile-Volatile-Fused Compute-In-Memory Macro Based on Logic-Compatible Flash for Plastic Neural Networks
errIEEE Journal of Solid-State Circuits
IF5.6
err2026-01-28
err0
PREAI
errWeizeng Li; Linfang Wang; Zhidao Zhou; Zhi Li; Wang Ye; Junyu Zhu; Junzhe Shen; Bohan Wang; Hanghang Gao; Hongyang Hu; Jing Liu; Jinshan Yue; Jianguo Yang; Qing Luo; Qi Liu; Chunmeng Dou; Yang Chai; Ming Liu
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Improved Reliability of Short-Channel IGZO TFTs With Hydrogen Scavenger Gate Metal
errIEEE Electron Device Letters
IF4.5
err2025-12-18
err0
PREAI
errZihan Li; Menggan Liu; Guanhua Yang; Fuxi Liao; Kaifei Chen; Xuanming Zhang; Naide Mao; Congyan Lu; Jiebin Niu; Jinshan Yue; Zhicheng Wu; Jiawei Wang; Lingfei Wang; Di Geng; Nianduan Lu; Arokia Nathan; Ling Li
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High-density three-dimensional integration of dynamic random-access memory using vertical dual-gate IGZO TFTs
errNature Communications
IF15.7
err2025-12-08
err0
errOAAI
errFuxi Liao; Zhengyong Zhu; Zihan Li; Guanhua Yang; Menggan Liu; Kaifei Chen; Wendong Lu; Zijing Wu; Xuanming Zhang; Naide Mao; Bok-Moon Kang; Jinghong Shi; Xie-Shuai Wu; Meichen Jin; Chang liu; Jing Zhang; Yong Yu; Gui-Lei Wang; Congyan Lu; Jinshan Yue; Lingfei Wang; Jiawei Wang; Di Geng; Nianduan Lu; Chao Zhao; Arokia Nathan; Ling Li; Ming Liu
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An area/energy-efficient RRAM computing-in-memory macro with fully-charge-domain multi-bit computation
errScience China Information Sciences
IF7.6
err2025-11-18
err0
PREAI
errZhi Li; Shengzhe Yan; Jun Wang; Zhuoyu Dai; Zeyu Guo; Zhaori Cong; Zhihang Qian; Xiangqu Fu; Xu Zheng; Chunmeng Dou; Dashan Shang; Jinshan Yue
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A 28-nm Computing-in-Memory Processor With Zig-Zag Backbone-Systolic CIM and Block-/Self-Gating CAM for NN/Recommendation Applications
errIEEE Journal of Solid-State Circuits
IF5.6
err2025-09-22
err0
PREAI
errShengzhe Yan; Zhuoyu Dai; Zhaori Cong; Zeyu Guo; Yifan He; Wenyu Sun; Chunmeng Dou; Feng Zhang; Jinshan Yue; Yongpan Liu; Ming Liu
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errSave
An Area-Efficient Lookup-Table -Based eDRAM Digital CIM Macro for Neural Network Inference
errIEEE Journal of Solid-State Circuits
IF5.6
err2025-08-18
err0
PREAI
errYifan He; Shupei Fan; Xuan Li; Luchang Lei; Wenbin Jia; Chen Tang; Yaolei Li; Zongle Huang; Zhike Du; Jinshan Yue; Xueqing Li; Huazhong Yang; Hongyang Jia; Yongpan Liu
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A 28-nm 88.3-TFLOPS/W POSIT-Approximate-Calculation-Based Digital Computing-in-Memory Macro Incorporating Final-Cycle Fusion and Joint Skipping
errIEEE Journal of Solid-State Circuits
IF5.6
err2025-08-05
err0
PREAI
errHao Wu; Yong Chen; Ming Li; Bingxin Zhang; Rui Zhang; Yiyang Yuan; Yiming Yang; Jinshan Yue; Xinghua Wang; Xiaoran Li; Feng Zhang
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A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications
errIEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF3.1
err2025-08-01
err0
PREAI
errJun Wang; Shengzhe Yan; Xiangqu Fu; Zhihang Qian; Zhi Li; Zeyu Guo; Zhuoyu Dai; Zhaori Cong; Chunmeng Dou; Feng Zhang; Jinshan Yue; Dashan Shang
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errSave
An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet
errIEEE Transactions on Very Large Scale Integration (VLSI) Systems
IF3.1
err2025-07-01
err0
PREAI
errZhihang Qian; Shengzhe Yan; Zhuoyu Dai; Zeyu Guo; Zhaori Cong; Yifan He; Chunmeng Dou; Feng Zhang; Jinshan Yue; Yongpan Liu
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errSave
Hybrid SRAM/ROM Compute-in-Memory Architecture for High Task-Level Energy Efficiency in Transformer Models With 8928-kb/mm² Density in 28nm CMOS
errIEEE Journal of Solid-State Circuits
IF5.6
err2025-04-15
err0
PREAI
errGuodong Yin; Yiming Chen; Mingyen Lee; Xirui Du; Yue Ke; Wenjun Tang; Zhonghao Chen; Mufeng Zhou; Jinshan Yue; Huazhong Yang; Hongyang Jia; Yongpan Liu; Xueqing Li
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A monolithic 3D IGZO-RRAM-SRAM-integrated architecture for robust and efficient compute-in-memory enabling equivalent-ideal device metrics
errSCIENCE CHINA-INFORMATION SCIENCES
IF7.6
err2025-01-15
err0
PREAI
errYan, Shengzhe; Cong, Zhaori; Wang, Zi; Dai, Zhuoyu; Guo, Zeyu; Qian, Zhihang; Li, Xufan; Zheng, Xu; Chen, Chuanke; Lu, Nianduan; Dou, Chunmeng; Yang, Guanhua; Xu, Xiaoxin; Geng, Di; Yue, Jinshan; Li, Ling; Liu, Ming
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Hardware Implementation of Next Generation Reservoir Computing with RRAM-Based Hybrid Digital-Analog System
errADVANCED INTELLIGENT SYSTEMS
IF6.1
err2024-07-03
err0
errOAAI
errDong, Danian; Zhang, Woyu; Xie, Yuanlu; Yue, Jinshan; Ren, Kuan; Huang, Hongjian; Zheng, Xu; Sun, Wen Xuan; Lai, Jin Ru; Fan, Shaoyang; Wang, Hongzhou; Yu, Zhaoan; Yao, Zhihong; Xu, Xiaoxin; Shang, Dashan; Liu, Ming
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2T2R RRAM-Based In-Memory Hyperdimensional Computing Encoder for Spatio-Temporal Signal Processing
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2024-05-01
err0
PREAI
errLi, Zhi; Bao, Rui; Zhang, Woyu; Wang, Fei; Wang, Jun; Fang, Renrui; Ren, Haoxiong; Lin, Ning; Yue, Jinshan; Dou, Chunmeng; Wang, Zhongrui; Shang, Dashan
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Fully Binarized Graph Convolutional Network Accelerator Based on In-Memory Computing with Resistive Random-Access Memory
errADVANCED INTELLIGENT SYSTEMS
IF6.1
err2024-03-25
err0
errOAAI
errZhang, Woyu; Li, Zhi; Zhang, Xinyuan; Wang, Fei; Wang, Shaocong; Lin, Ning; Li, Yi; Wang, Jun; Yue, Jinshan; Dou, Chunmeng; Xu, Xiaoxin; Wang, Zhongrui; Shang, Dashan
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A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
IF5.2
err2024-02-01
err1
PREAI
errWu, Hao; Chen, Yong; Yuan, Yiyang; Yue, Jinshan; Fu, Xiangqu; Ren, Qirui; Luo, Qing; Mak, Pui-In; Wang, Xinghua; Zhang, Feng
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LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design
errIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
IF4.9
err2024-02-01
err2
PREAI
errHe, Chaojie; Wang, Zi; Xiang, Feibin; Dai, Zhuoyu; He, Yifan; Yue, Jinshan; Liu, Yongpan
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Research Directions

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Co-authors
Cooperation Journals
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刘琦 (Qi Liu)
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王君 (Jun Wang)
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刘明 (Ming Liu)
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王飞 (Fei Wang)
H-index: 77 · Papers: 1.0K
Z
Zhongrui Wang
H-index: 60 · Papers: 372
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