Extraction of Device Structural Parameters Through DC/AC Performance Using an MLP Neural Network Algorithm

Hyundong Jang

doi:10.1109/ACCESS.2022.3183803

Extraction of Device Structural Parameters Through DC/AC Performance Using an MLP Neural Network Algorithm

2022-01-01

2

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AI

DOI：10.1109/ACCESS.2022.3183803

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We proposed a neural network (NN) approach that uses two multi-layer perceptron (MLP) NNs an encoder and a decoder to estimate the structural parameter (S-para) of a 14-nm node fully depleted silicon on insulator (FDSOI) field-effect transistor (FET). When outputs defined by the same input exist, the proposed NN algorithm achieves loss function convergence during NN training. The decoder takes inputs of on/off current ratio, delay, and power to represent DC/AC performance for high performance (HP), low operating power (LOP), and low standby power (LSTP) applications. With the pre-trained encoder learned with R coefficients of the regression plot over 0.99 and an average percent error of approximately 1%, the decoder was modeled to estimate the S-para. Our decoder successfully estimated all S-para within the range that satisfies the technology node. The tendency of S-para satisfying the desired figure-of-merits (FOMs) in device design can be confirmed by comparing the estimated S-para of the upper 5 % and 10 % cases. Furthermore, it can provide device design guidance from various perspectives by presenting numerous alternatives of distinct S-para sets, even when the FOM value is the same (duplicate input values). If undesirable FOMs are extracted, it is possible to determine the causal S-para and provide immediate process feedback on the related unit process using the S-para estimated from the lower 5 % of FOMs. We performed a detailed physical analysis as an example of a delay in LOP application. NN estimation results were analyzed using gate length (L-g), SOI thickness (T-soi), and drain-side spacer length (L-spd), which mainly affect gate capacitance (C-g) and effective current (I-eff). In addition, source-side spacer length (L-sps) and source/drain junction gradient (L-sdj) showed behaviors different from those generally selected by human experts and cases where maximal values were not estimated within the set range. The estimation of S-para using the NN was effective and powerful, reducing process cost and feedback time.

Keyword:

Device design

device structural parameters

FDSOI FET

figure-of-merits

machine learning

manufacturing process

MLP

14-nm node

Extraction of Device Structural Parameters Through DC/AC Performance Using an MLP Neural Network Algorithm

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